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march 2015 docid025619 rev 2 1 / 13 this is information on a product in full production. www.st.com STS7P4LLF6 p - channel 40 v, 0.0175 typ.,7 a, stripfet? f6 power mosfet in an so - 8 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STS7P4LLF6 40 v 0.0205 7 a ? very low on - resistance ? very low gate charge ? high avalanche ruggedness ? low gate drive power loss applications ? switching applications description this device is a p - channel power mosfet developed using the stripfet? f6 technology, with a new trench gate structure. the resulting power mosfet exhibits very low r ds(on) in all packages. for the p - channel power mosfet, current polarity of voltages and current have to be reversed. table 1: device summary order code marking package packaging STS7P4LLF6 7k4l so -8 tape and reel
contents STS7P4LLF6 2 / 13 docid025619 rev 2 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.1 electrical characteristics (curves) ...................................................... 6 3 test circuits ..................................................................................... 8 4 package information ....................................................................... 9 4.1 so - 8 package information ................................................................ 9 4.2 packing information ......................................................................... 11 5 revision history ............................................................................ 12
STS7P4LLF6 electrical ratings docid025619 rev 2 3 / 13 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - source voltage 40 v v gs gate - source voltage 20 v i d drain current (continuous) at t amb = 25 c 7 a i d drain current (continuous) at t amb = 100 c 4.2 a i dm (1) drain current (pulsed) 28 a p tot total dissipation at t amb = 25 c 2.7 w t stg storage temperature - 55 to 150 c t j maximum junction temperature 150 c notes: (1) pulse width limited by safe operating area. table 3: thermal data symbol parameter value unit r thj - amb (1) thermal resistance junction - amb 47 c/w notes: (1) when mounted on 1 inch2 fr - 4 board, 2 oz. cu., t 10 s for the p - channel power mosfet, current polarity of voltages and current have to be reversed.
electrical characteristics STS7P4LLF6 4 / 13 docid025619 rev 2 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4: static symbol parameter test conditions min . typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 250 a 40 v i dss zero gate voltage drain current v gs = 0 v, v ds = 40 v 1 a v gs = 0 v, v ds = 40 v, t c = 125 c 10 a i gss gate - body leakage current v ds = 0 v, v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 3.5 a 0.0175 0.0205 v gs = 4.5 v, i d = 3.5 a 0.0205 0.029 table 5: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 25 v, f = 1 mhz, v gs = 0 v - 2850 - pf c oss output capacitance - 270 - pf c rss reverse transfer capacitance - 180 - pf q g total gate charge v dd = 20 v, i d = 7 a, v gs = 4.5 v (see figure 14: "gate charge test circuit" ) - 22 - nc q gs gate - source charge - 9.4 - nc q gd gate - drain charge - 7.3 - nc r g gate input resistance i d = 0 a, gate dc bias = 0 v, f = 1 mhz, magnitude of alternative signal = 20 mv - 1.4 - table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 20 v, i d = 3.5 a r g = 4.7 , v gs = 10 v (see figure 13: "switching times test circuit for resistive load" ) - 43 - ns t r rise time - 47 - ns t d(off) turn - off- delay time - 148 - ns t f fall time - 19 - ns for the p - channel power mosfet, current polarity of voltages and current have to be reversed.
STS7P4LLF6 electric al characteristics docid025619 rev 2 5 / 13 table 7: source drain diode symbol parameter test conditions min. typ. max. unit v sd (1) forward on voltage v gs = 0 v, i sd = 3.5 a - 1.1 v t rr reverse recovery time i sd = 3.5 a, di/dt = 100 a/s, v dd = 32 v, t j = 150 c (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 26 ns q rr reverse recovery charge - 21 nc i rrm reverse recovery current - 1.7 a notes: (1) pulse test: pulse duration = 300 s, duty cycle 1.5% for the p - channel power mosfet, current polarity of voltages and current have to be reversed.
electrical characteristics STS7P4LLF6 6 / 13 docid025619 rev 2 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : normalized gate threshold voltage vs temperature figure 7 : normalized v(br)dss vs temperature
STS7P4LLF6 electrical characteristics docid025619 rev 2 7 / 13 figure 8 : static drain - source on - resistance figure 9 : normalized on - resistance vs. temperature figure 10 : gate charge vs gate - source voltage figure 11 : capacitance variations voltage figure 12 : source - drain diode forward characteristics
test circuits STS7P4LLF6 8 / 13 docid025619 rev 2 3 test circuits figure 13 : switching times test circuit for resistive load figure 14 : gate charge test circuit figure 15 : test circuit for inductive load switching and diode recovery times
STS7P4LLF6 package information docid025619 rev 2 9 / 13 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an s t trademark. 4.1 so- 8 package information figure 16 : so - 8 package outline
package information STS7P4LLF6 10 / 13 docid025619 rev 2 table 8: so - 8 mechanical data dim. mm min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b 0.31 0.51 b1 0.28 0.48 c 0.10 0.25 c1 0.10 0.23 d 4.80 4.90 5.00 e 5.80 6.00 6.20 e1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 l 0.40 1.27 l1 1.04 l2 0.25 k 0 8 ccc 0.10 figure 17 : so - 8 recommended footprint
STS7P4LLF6 package information docid025619 rev 2 11 / 13 4.2 p acking information figure 18 : so -8 tape and reel dimension s table 9: so - 8 tape and reel mechanical data dim. mm min. typ. max. a - 330 c 12.8 13.2 d 20.2 n 60 t 22.4 ao 8.1 8.5 bo 5.5 5.9 ko 2.1 2.3 po 3.9 4.1 p 7.9 8.1
revision history STS7P4LLF6 12 / 13 docid025619 rev 2 5 revision history table 10: document revision history date revision changes 10- dec - 2013 1 first revision. 10- mar -2015 2 text edits throughout document on cover page, updated title, description and features table updated and renamed table 4: static updated table 5: dynamic updated table 6: switching times updated table 7: source - drain diode added section 2.1: electrical characteristics (curves) minor text changes
STS7P4LLF6 docid025619 rev 2 13 / 13 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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